Integrated semiconductor circuits, particularly systems or arrays having transistors each of which represents a binary digit of information, as in read only memories (ROM), have achieved high device or cell densities.
In, e.g., U.S. Pat. No. 3,914,855, filed May 9, 1974 there is described a read only memory wherein the array has transistors made with a thin gate dielectric exhibiting a low threshold voltage for storing a 1 digit of binary information and transistors made of a thick gate dielectric exhibiting a considerably higher threshold voltage for storing the other digit of binary information. This patent also describes a read only memory wherein the array is encoded by etching apertures in the gate electrodes of selected devices and implanting ion impurities through the apertures to render the selected devices inoperative, as defining a 1 digit of binary information, while the remaining devices which do not have apertures in the gate electrode are operative devices or transistors defining the other digit of binary information.
A read only memory disclosed in U.S. Pat. No. 4,096,522, filed Aug. 8, 1977 is personalized by completing connections between selected source and drain electrodes and the channel regions of the transistors.
In U.S. Pat. No. 4,161,039, filed Feb. 6, 1978, there is disclosed a memory array utilizing field effect transistors (FET) where information is stored in floating gates and the channel region is made short by employing double-diffusion processing techniques, as disclosed in more detail in "Electronics", Feb. 15, 1971, at pages 99-104. This memory is not a simple read only memory but one that can be reprogrammed by erasing the stored information with ultraviolet light.
Commonly assigned U.S. Pat. No. 3,972,059, filed Dec. 28, 1973 by T. H. DiStefano discloses a charge store FET memory suitable for operation in a read only mode which includes a floating gate and a write gate separated by a first insulating layer having a low band gap at the write gate and an erase gate separated from the floating gate by a second insulating layer having a low band gap at the floating gate.
Commonly assigned U.S. Pat. No. 4,104,675, filed June 21, 1977 by D. J. DiMaria et al discloses a non-destructive long-term storage system using a single graded energy band gap structure in each cell which may be driven by a low voltage.
In IBM Technical Disclosure Bulletin Vol. 22 No. 6 November 1979 pp. 2403-2404 there is described another floating gate non-volatile memory cell having a split control gate.
In commonly assigned U.S. patent application Ser. No. 124,003 filed Feb. 25, 1980 by D. J. DiMaria there is disclosed a non-destructive long-term storage system using a dual charge injector or dual graded energy band gap structure in each cell which is driven by a low voltage.
In U.S. Pat. No. 3,825,946, filed Oct. 19, 1973 there is disclosed an electrically alterable floating gate storage or memory device having two control gates, one being used for writing and the other being used for erasing. A common positive voltage is alterably applied to the two control gates for writing and erasing.